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| author | whitequark <whitequark@whitequark.org> | 2021-02-04 09:57:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-04 09:57:28 +0000 |
| commit | baf1875307f1608762169d3037ba005da88b201e (patch) | |
| tree | 44b84ab2ef42251cdc916a417e105c3f172c2a19 /techlibs/xilinx | |
| parent | afcc31ceba35d33fc11f9e1592956bb4112ca0e3 (diff) | |
| parent | fe74b0cd95267bc78953236311382653a6db7f60 (diff) | |
| download | yosys-baf1875307f1608762169d3037ba005da88b201e.tar.gz yosys-baf1875307f1608762169d3037ba005da88b201e.tar.bz2 yosys-baf1875307f1608762169d3037ba005da88b201e.zip | |
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index eb8a04bde..63be7563e 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -151,6 +151,8 @@ generate if (`LUT_SIZE == 4) begin ); end endgenerate + assign X = S; + end else begin localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; @@ -193,8 +195,8 @@ end else begin end end endgenerate -end endgenerate - assign X = S; + +end endgenerate endmodule |