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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 08:59:17 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 08:59:17 -0800 |
| commit | c3262d60752bb20ff5cd54bc4ee6f56e2b772b05 (patch) | |
| tree | e374a9aef2a73e907f49e916090b761575e69c90 /techlibs/xilinx | |
| parent | d6514fc2e13976b15be396f413b046deb6f0c9fa (diff) | |
| download | yosys-c3262d60752bb20ff5cd54bc4ee6f56e2b772b05.tar.gz yosys-c3262d60752bb20ff5cd54bc4ee6f56e2b772b05.tar.bz2 yosys-c3262d60752bb20ff5cd54bc4ee6f56e2b772b05.zip | |
Disable RAM16X1D match rule; carry-over from LUT4 arches
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/lutrams.txt | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index be764a63f..ae629bce8 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -105,12 +105,15 @@ bram $__XILINX_RAM64M endbram -match $__XILINX_RAM16X1D - min bits 2 - min wports 1 - make_outreg - or_next_if_better -endmatch +# Disabled for now, pending support for LUT4 arches +# since on LUT6 arches this occupies same area as +# a RAM32X1D +#match $__XILINX_RAM16X1D +# min bits 2 +# min wports 1 +# make_outreg +# or_next_if_better +#endmatch match $__XILINX_RAM32X1D min bits 3 |