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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 09:04:20 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-13 09:04:20 -0800 |
| commit | ca2f3db53f3f330d283079bf44b3cef6b7f197be (patch) | |
| tree | b633788b56a0575be8f70644641c352adb1a653e /techlibs/xilinx | |
| parent | 0f489c5ea340869206888c6f1feb672b7202b185 (diff) | |
| parent | 35e49fde4dfa67030a3e80d0bdf700c97258ed45 (diff) | |
| download | yosys-ca2f3db53f3f330d283079bf44b3cef6b7f197be.tar.gz yosys-ca2f3db53f3f330d283079bf44b3cef6b7f197be.tar.bz2 yosys-ca2f3db53f3f330d283079bf44b3cef6b7f197be.zip | |
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad
abc9: add some scripts/options into "scratchpad"
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 63d00027a..d916093dc 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -26,13 +26,16 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate - // to one LUT6 (instead of a LUT5 + LUT2) - struct SynthXilinxPass : public ScriptPass { SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { } + void on_register() YS_OVERRIDE + { + RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate + // to one LUT6 (instead of a LUT5 + LUT2) + } + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -555,7 +558,11 @@ struct SynthXilinxPass : public ScriptPass run("techmap " + techmap_args); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; - abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); + auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); + if (active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else |