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authorEddie Hung <eddie@fpgeh.com>2019-04-26 16:28:48 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-26 16:28:48 -0700
commitccc283737d99cb0f4d5742692d5d86c4ad9396c6 (patch)
treefaeb7665cb3703c2bea1eb9478236dc2f29a7afa /techlibs/xilinx
parente31e21766d3bf323ce61754a28ac58ec7118b9c0 (diff)
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Apparently, this reduces number of MUXCY/XORCY
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc19
1 files changed, 9 insertions, 10 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5652806f7..4ec115bec 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -287,11 +287,18 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "fine"))
{
- Pass::call(design, "opt -fast");
+ Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
Pass::call(design, "dffsr2dff");
Pass::call(design, "dff2dffe");
+ if (!nocarry) {
+ if (vpr)
+ Pass::call(design, "techmap -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
+ else
+ Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+ }
+
// shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifying variable-length shift registers,
// so attempt to convert $pmux-es to the former
@@ -300,15 +307,7 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "pmux2shiftx");
Pass::call(design, "opt -full");
- if (!nocarry) {
- if (vpr)
- Pass::call(design, "techmap -map +/techmap.v -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
- else
- Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
- }
- else {
- Pass::call(design, "techmap");
- }
+ Pass::call(design, "techmap");
Pass::call(design, "opt -fast");
// shregmap with '-tech xilinx' infers variable length shift regs