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| author | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-09-22 11:35:04 +0200 |
|---|---|---|
| committer | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-09-22 11:35:04 +0200 |
| commit | d3c67ad9b61f602de1100cd264efd227dcacb417 (patch) | |
| tree | 88c462c53bdab128cd1edbded42483772f82612a /techlibs/xilinx | |
| parent | b783dbe148e6d246ebd107c0913de2989ab5af48 (diff) | |
| parent | 13117bb346dd02d2345f716b4403239aebe3d0e2 (diff) | |
| download | yosys-d3c67ad9b61f602de1100cd264efd227dcacb417.tar.gz yosys-d3c67ad9b61f602de1100cd264efd227dcacb417.tar.bz2 yosys-d3c67ad9b61f602de1100cd264efd227dcacb417.zip | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation
Conflicts:
backends/btor/btor.cc
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 4 | ||||
| -rw-r--r-- | techlibs/xilinx/cells.v | 36 |
2 files changed, 20 insertions, 20 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index f88390f73..cd19f10e7 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -4,6 +4,6 @@ OBJS += techlibs/xilinx/synth_xilinx.o EXTRA_TARGETS += share/xilinx/cells.v share/xilinx/cells.v: techlibs/xilinx/cells.v - mkdir -p share/xilinx - cp techlibs/xilinx/cells.v share/xilinx/cells.v + $(P) mkdir -p share/xilinx + $(Q) cp techlibs/xilinx/cells.v share/xilinx/cells.v diff --git a/techlibs/xilinx/cells.v b/techlibs/xilinx/cells.v index 5bf8ccd86..d19be0db7 100644 --- a/techlibs/xilinx/cells.v +++ b/techlibs/xilinx/cells.v @@ -10,41 +10,41 @@ module \$_DFF_P_ (D, C, Q); endmodule -module \$lut (I, O); +module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; - input [WIDTH-1:0] I; - output O; + input [WIDTH-1:0] A; + output Y; generate if (WIDTH == 1) begin:lut1 - LUT1 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0])); + LUT1 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0])); end else if (WIDTH == 2) begin:lut2 - LUT2 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1])); + LUT2 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1])); end else if (WIDTH == 3) begin:lut3 - LUT3 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2])); + LUT3 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2])); end else if (WIDTH == 4) begin:lut4 - LUT4 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2]), - .I3(I[3])); + LUT4 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3])); end else if (WIDTH == 5) begin:lut5 - LUT5 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2]), - .I3(I[3]), .I4(I[4])); + LUT5 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4])); end else if (WIDTH == 6) begin:lut6 - LUT6 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2]), - .I3(I[3]), .I4(I[4]), .I5(I[5])); + LUT6 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); end else begin:error wire _TECHMAP_FAIL_ = 1; end |