diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 14:25:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 14:25:40 -0700 |
| commit | e3f8e59f182129aa2ff9ba7a1ed7fbbaab657ce5 (patch) | |
| tree | 68697b51d9a9f9b31c7e7830155e359d2c65b2c1 /techlibs/xilinx | |
| parent | 58e63feae1e950fff839c4261a787d5daf07612e (diff) | |
| download | yosys-e3f8e59f182129aa2ff9ba7a1ed7fbbaab657ce5.tar.gz yosys-e3f8e59f182129aa2ff9ba7a1ed7fbbaab657ce5.tar.bz2 yosys-e3f8e59f182129aa2ff9ba7a1ed7fbbaab657ce5.zip | |
Make all operands signed
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 28e456898..32f570935 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); +module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); wire [47:0] P_48; DSP48E1 #( // Disable all registers |