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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-09 16:56:29 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-09 16:56:29 +0200 |
| commit | ef07a313b4122b9ceb233ed7dd4733db97272577 (patch) | |
| tree | ef7570bb5a462e44cc40da51894917db7ff4a76a /techlibs/xilinx | |
| parent | a429aedc0ff21b95ded89320144d2063234a3d7e (diff) | |
| parent | 93bc5affd3fc635dafec3a37bf4c5b94c252036f (diff) | |
| download | yosys-ef07a313b4122b9ceb233ed7dd4733db97272577.tar.gz yosys-ef07a313b4122b9ceb233ed7dd4733db97272577.tar.bz2 yosys-ef07a313b4122b9ceb233ed7dd4733db97272577.zip | |
Merge pull request #1162 from whitequark/rtlil-case-attrs
Allow attributes on individual switch cases in RTLIL
Diffstat (limited to 'techlibs/xilinx')
0 files changed, 0 insertions, 0 deletions