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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-02 15:01:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-02 15:01:37 -0700 |
| commit | fc72f07efdfbc1b87c4838af6138cdaa3cfd97ff (patch) | |
| tree | c259c4512424ff04f9c2d125d9a049237b6e0bf8 /techlibs/xilinx | |
| parent | d80445e0492c67b63435880b3bca4ccbf6f3db43 (diff) | |
| download | yosys-fc72f07efdfbc1b87c4838af6138cdaa3cfd97ff.tar.gz yosys-fc72f07efdfbc1b87c4838af6138cdaa3cfd97ff.tar.bz2 yosys-fc72f07efdfbc1b87c4838af6138cdaa3cfd97ff.zip | |
Add don't care optimisation
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 0ec72b6a4..ecfbe2555 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -161,11 +161,14 @@ module \$shiftx (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0; + parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; generate genvar i, j; + // TODO: Check if this opt still necessary if (B_SIGNED) begin if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) // Optimisation to remove B_SIGNED if sign bit of B is constant-0 @@ -186,6 +189,14 @@ module \$shiftx (A, B, Y); assign A_i[i] = A[i*2]; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end + // If upper half of A input is all constant 1'bx then + // chop this $shiftx in half + else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1:2**(B_WIDTH-1)] == {A_WIDTH-2**(B_WIDTH-1){1'b1}} && _TECHMAP_CONSTVAL_A_[A_WIDTH-1:2**(B_WIDTH-1)] === {A_WIDTH-2**(B_WIDTH-1){1'bx}}) begin + if (B_WIDTH > 1) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-1)), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[2**(B_WIDTH-1)-1:0]), .B(B[B_WIDTH-2:0]), .Y(Y)); + else + assign Y = A[0]; + end else if (B_WIDTH < 3 || A_WIDTH <= 4) begin wire _TECHMAP_FAIL_ = 1; end |