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| author | Xiretza <xiretza@xiretza.xyz> | 2021-03-18 10:38:36 +0100 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-14 13:56:51 -0400 |
| commit | b57e47fad8b4ecd5438ee49c618fc8978a4bb058 (patch) | |
| tree | 73f6363ebdc0b6683c52ccd5c1a864d76fc42e70 /tests/aiger/empty.aig | |
| parent | 62a42c317c41590b654f59851b4730c89bfcd7ae (diff) | |
| download | yosys-b57e47fad8b4ecd5438ee49c618fc8978a4bb058.tar.gz yosys-b57e47fad8b4ecd5438ee49c618fc8978a4bb058.tar.bz2 yosys-b57e47fad8b4ecd5438ee49c618fc8978a4bb058.zip | |
verilog: fix wildcard port connections leaking memory
Diffstat (limited to 'tests/aiger/empty.aig')
0 files changed, 0 insertions, 0 deletions