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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-07 12:30:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-07 12:30:52 +0200 |
| commit | 4c49ddf36af217d0dfa7dbd9d7e24b4dbc388ba9 (patch) | |
| tree | 3247c746f2982ff7ce557d045b1c88eda0cb7089 /tests/aiger/false.aig | |
| parent | 679bc6507f08cab33de0c46b3a96bfaeab2069f4 (diff) | |
| parent | 837cb0a1b9c9a774512481d0812c28f927985e7b (diff) | |
| download | yosys-4c49ddf36af217d0dfa7dbd9d7e24b4dbc388ba9.tar.gz yosys-4c49ddf36af217d0dfa7dbd9d7e24b4dbc388ba9.tar.bz2 yosys-4c49ddf36af217d0dfa7dbd9d7e24b4dbc388ba9.zip | |
Merge pull request #1249 from mmicko/anlogic_fix
anlogic : Fix alu mapping
Diffstat (limited to 'tests/aiger/false.aig')
0 files changed, 0 insertions, 0 deletions