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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:04 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:04 +0200 |
| commit | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (patch) | |
| tree | a78b5d92952ea9f95623bb3daf8028d2402d023b /tests/anlogic/fsm.v | |
| parent | 5ffb0053ec7d53ffc5c57e3277bfbab5d3fddb54 (diff) | |
| parent | 66fca65b58bfb944cad45da5836613726498e4b7 (diff) | |
| download | yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.gz yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.bz2 yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.zip | |
Merge pull request #1434 from YosysHQ/mmicko/anlogic
Add tests for Anlogic architecture (contd)
Diffstat (limited to 'tests/anlogic/fsm.v')
| -rw-r--r-- | tests/anlogic/fsm.v | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v new file mode 100644 index 000000000..368fbaace --- /dev/null +++ b/tests/anlogic/fsm.v @@ -0,0 +1,55 @@ + module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input clock,reset,req_0,req_1;
+ output gnt_0,gnt_1;
+ wire clock,reset,req_0,req_1;
+ reg gnt_0,gnt_1;
+
+ parameter SIZE = 3 ;
+ parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+ end else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT0;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT2;
+ gnt_1 <= req_0;
+ end
+ GNT2 : if (req_0 == 1'b1) begin
+ state <= #1 GNT1;
+ gnt_1 <= req_1;
+ end
+ default : state <= #1 IDLE;
+ endcase
+ end
+
+endmodule
|