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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:04 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:04 +0200 |
| commit | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (patch) | |
| tree | a78b5d92952ea9f95623bb3daf8028d2402d023b /tests/anlogic/memory.v | |
| parent | 5ffb0053ec7d53ffc5c57e3277bfbab5d3fddb54 (diff) | |
| parent | 66fca65b58bfb944cad45da5836613726498e4b7 (diff) | |
| download | yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.gz yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.bz2 yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.zip | |
Merge pull request #1434 from YosysHQ/mmicko/anlogic
Add tests for Anlogic architecture (contd)
Diffstat (limited to 'tests/anlogic/memory.v')
| -rw-r--r-- | tests/anlogic/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/anlogic/memory.v b/tests/anlogic/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/anlogic/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule |