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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:04 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:04 +0200 |
| commit | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (patch) | |
| tree | a78b5d92952ea9f95623bb3daf8028d2402d023b /tests/anlogic/memory.ys | |
| parent | 5ffb0053ec7d53ffc5c57e3277bfbab5d3fddb54 (diff) | |
| parent | 66fca65b58bfb944cad45da5836613726498e4b7 (diff) | |
| download | yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.gz yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.bz2 yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.zip | |
Merge pull request #1434 from YosysHQ/mmicko/anlogic
Add tests for Anlogic architecture (contd)
Diffstat (limited to 'tests/anlogic/memory.ys')
| -rw-r--r-- | tests/anlogic/memory.ys | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/anlogic/memory.ys b/tests/anlogic/memory.ys new file mode 100644 index 000000000..8c0ce844e --- /dev/null +++ b/tests/anlogic/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D |