diff options
author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:28 +0200 |
---|---|---|
committer | GitHub <noreply@github.com> | 2019-10-18 10:54:28 +0200 |
commit | b4d765054897f7ee388b54d907fd8ce607db2d58 (patch) | |
tree | a625838a0efbfb0176a57887c208467a7addd0a6 /tests/anlogic/mux.v | |
parent | b659082e4a72209af62a19668800bb6334a437d7 (diff) | |
parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
download | yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.gz yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.bz2 yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.zip |
Merge branch 'master' into mmicko/efinix
Diffstat (limited to 'tests/anlogic/mux.v')
-rw-r--r-- | tests/anlogic/mux.v | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/anlogic/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule |