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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 12:46:18 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 12:46:18 -0800 |
| commit | a855f23f22c9e6dbba5ff17a9541a7d26342b56a (patch) | |
| tree | f62715ee5a790615d8d4fcda7814a940608c7310 /tests/arch/anlogic/counter.ys | |
| parent | f5e0a07ad679696b0d3077ef877941d4c1f864d7 (diff) | |
| parent | 7939727d14f44b5d56ca3806d0907e9fceea2882 (diff) | |
| download | yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.tar.gz yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.tar.bz2 yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.zip | |
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
Diffstat (limited to 'tests/arch/anlogic/counter.ys')
| -rw-r--r-- | tests/arch/anlogic/counter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys index d363ec24e..a6eab248c 100644 --- a/tests/arch/anlogic/counter.ys +++ b/tests/arch/anlogic/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |