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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 12:46:18 -0800 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 12:46:18 -0800 |
| commit | a855f23f22c9e6dbba5ff17a9541a7d26342b56a (patch) | |
| tree | f62715ee5a790615d8d4fcda7814a940608c7310 /tests/arch/anlogic/lutram.ys | |
| parent | f5e0a07ad679696b0d3077ef877941d4c1f864d7 (diff) | |
| parent | 7939727d14f44b5d56ca3806d0907e9fceea2882 (diff) | |
| download | yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.tar.gz yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.tar.bz2 yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.zip | |
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
Diffstat (limited to 'tests/arch/anlogic/lutram.ys')
| -rw-r--r-- | tests/arch/anlogic/lutram.ys | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys new file mode 100644 index 000000000..9ebb75443 --- /dev/null +++ b/tests/arch/anlogic/lutram.ys @@ -0,0 +1,21 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D |