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authorMiodrag Milanovic <mmicko@gmail.com>2019-10-18 11:06:12 +0200
committerMiodrag Milanovic <mmicko@gmail.com>2019-10-18 11:06:12 +0200
commitc2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch)
tree79cce7951390a0068beeab26be5d310222059c51 /tests/arch/anlogic/mux.v
parent3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff)
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Moved all tests in arch sub directory
Diffstat (limited to 'tests/arch/anlogic/mux.v')
-rw-r--r--tests/arch/anlogic/mux.v65
1 files changed, 65 insertions, 0 deletions
diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v
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+++ b/tests/arch/anlogic/mux.v
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+module mux2 (S,A,B,Y);
+ input S;
+ input A,B;
+ output reg Y;
+
+ always @(*)
+ Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ 4 : Y = D[4];
+ 5 : Y = D[5];
+ 6 : Y = D[6];
+ 7 : Y = D[7];
+ endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ input [15:0] D;
+ input [3:0] S;
+ output Y;
+
+assign Y = D[S];
+
+endmodule