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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-16 12:43:17 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-16 12:43:17 +0100 |
| commit | 32f0296df1b97ff5b3bcc442ac38f27a786947d6 (patch) | |
| tree | 72ec224a90bb5a40e007a88fe37085dcc786a0e0 /tests/arch/anlogic | |
| parent | ab8c521030a2c91a1e388d6f3c627a7f7dd525b2 (diff) | |
| parent | 51e4e29bb1f7c030b0cac351c522dc41f7587be2 (diff) | |
| download | yosys-32f0296df1b97ff5b3bcc442ac38f27a786947d6.tar.gz yosys-32f0296df1b97ff5b3bcc442ac38f27a786947d6.tar.bz2 yosys-32f0296df1b97ff5b3bcc442ac38f27a786947d6.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'tests/arch/anlogic')
| -rw-r--r-- | tests/arch/anlogic/fsm.ys | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys index f45951b13..0bcc4e011 100644 --- a/tests/arch/anlogic/fsm.ys +++ b/tests/arch/anlogic/fsm.ys @@ -1,12 +1,15 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc -#flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +flatten + +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module + select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 |