Unify verilog style

1 files changed, 25 insertions, 29 deletions

diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 223b52d21..576bd81a6 100644
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,47 +1,43 @@
-module adff
-    ( input d, clk, clr, output reg q );
+module adff( input d, clk, clr, output reg q );
     initial begin
-      q = 0;
+        q = 0;
     end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
+	  always @( posedge clk, posedge clr )
+      if ( clr )
+        q <= 1'b0;
+      else
+        q <= d;
 endmodule
 
-module adffn
-    ( input d, clk, clr, output reg q );
+module adffn( input d, clk, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
+	  always @( posedge clk, negedge clr )
+		  if ( !clr )
+			  q <= 1'b0;
+  		else
+        q <= d;
 endmodule
 
-module dffs
-    ( input d, clk, pre, clr, output reg q );
+module dffs( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
+    always @( posedge clk )
+      if ( pre )
+        q <= 1'b1;
+      else
+        q <= d;
 endmodule
 
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
+module ndffnr( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
+    always @( negedge clk )
+      if ( !clr )
+        q <= 1'b0;
+      else
+        q <= d;
 endmodule