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authorEddie Hung <eddie@fpgeh.com>2019-12-16 13:01:51 -0800
committerEddie Hung <eddie@fpgeh.com>2019-12-16 13:01:51 -0800
commite990c013c57da8149dbbd2fe2633e953ec8f471b (patch)
tree359aab88fc063ab153fefa41197f62151ae4cfb7 /tests/arch/common/blockram.v
parentd910bec8e00b5e9eba2fc62dec1a6b734e429cc4 (diff)
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Merge blockram tests
Diffstat (limited to 'tests/arch/common/blockram.v')
-rw-r--r--tests/arch/common/blockram.v45
1 files changed, 45 insertions, 0 deletions
diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v
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+`default_nettype none
+module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+ (input wire write_enable, clk,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in] <= data_in;
+ data_out_r <= memory[address_in];
+ end
+
+ assign data_out = data_out_r;
+endmodule // sync_ram_sp
+
+
+`default_nettype none
+module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+ (input wire clk, write_enable,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in_w] <= data_in;
+ data_out_r <= memory[address_in_r];
+ end
+
+ assign data_out = data_out_r;
+endmodule // sync_ram_sdp
+