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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
| commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
| tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/arch/common/counter.v | |
| parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
| parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
| download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/arch/common/counter.v')
| -rw-r--r-- | tests/arch/common/counter.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v new file mode 100644 index 000000000..9746fd701 --- /dev/null +++ b/tests/arch/common/counter.v @@ -0,0 +1,11 @@ +module top ( out, clk, reset );
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset)
+ out <= 8'b0;
+ else
+ out <= out + 1;
+endmodule
|