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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
| commit | 5603595e5c0efd2afc9ba810e6e5992e5d81d44c (patch) | |
| tree | dcf99c611410e055a7ea71c970938ed6ee50a3c6 /tests/arch/common/counter.v | |
| parent | ab98f2dccf52a1bba396fe313ea0670603dc45ca (diff) | |
| download | yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.gz yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.bz2 yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.zip | |
Share common tests
Diffstat (limited to 'tests/arch/common/counter.v')
| -rw-r--r-- | tests/arch/common/counter.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/common/counter.v @@ -0,0 +1,17 @@ +module top (
+out,
+clk,
+reset
+);
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset) begin
+ out <= 8'b0 ;
+ end else
+ out <= out + 1;
+
+
+endmodule
|