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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
| commit | 9bd9db56c8ef8ca413f97086fd53609c50df343b (patch) | |
| tree | 869984a858e5c9d502ccdfd800618a9c0fe5858a /tests/arch/common/counter.v | |
| parent | 12383f37b2e1d72784e01db0431efc8882f25430 (diff) | |
| download | yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.gz yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.bz2 yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.zip | |
Unify verilog style
Diffstat (limited to 'tests/arch/common/counter.v')
| -rw-r--r-- | tests/arch/common/counter.v | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 52852f8ac..97604d3d8 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -1,17 +1,11 @@ -module top (
-out,
-clk,
-reset
-);
+module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
- if (reset) begin
- out <= 8'b0 ;
- end else
- out <= out + 1;
-
-
+ if (reset)
+ out <= 8'b0;
+ end
+ out <= out + 1;
endmodule
|