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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
| commit | 9bd9db56c8ef8ca413f97086fd53609c50df343b (patch) | |
| tree | 869984a858e5c9d502ccdfd800618a9c0fe5858a /tests/arch/common/dffs.v | |
| parent | 12383f37b2e1d72784e01db0431efc8882f25430 (diff) | |
| download | yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.gz yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.bz2 yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.zip | |
Unify verilog style
Diffstat (limited to 'tests/arch/common/dffs.v')
| -rw-r--r-- | tests/arch/common/dffs.v | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v index 3418787c9..636252d16 100644 --- a/tests/arch/common/dffs.v +++ b/tests/arch/common/dffs.v @@ -1,15 +1,13 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; +module dff ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; endmodule -module dffe - ( input d, clk, en, output reg q ); +module dffe( input d, clk, en, output reg q ); initial begin - q = 0; + q = 0; end - always @( posedge clk ) - if ( en ) - q <= d; + always @( posedge clk ) + if ( en ) + q <= d; endmodule |