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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
commit | 5603595e5c0efd2afc9ba810e6e5992e5d81d44c (patch) | |
tree | dcf99c611410e055a7ea71c970938ed6ee50a3c6 /tests/arch/common/latches.v | |
parent | ab98f2dccf52a1bba396fe313ea0670603dc45ca (diff) | |
download | yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.gz yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.bz2 yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.zip |
Share common tests
Diffstat (limited to 'tests/arch/common/latches.v')
-rw-r--r-- | tests/arch/common/latches.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v new file mode 100644 index 000000000..adb5d5319 --- /dev/null +++ b/tests/arch/common/latches.v @@ -0,0 +1,24 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule |