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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
| commit | 9bd9db56c8ef8ca413f97086fd53609c50df343b (patch) | |
| tree | 869984a858e5c9d502ccdfd800618a9c0fe5858a /tests/arch/common/latches.v | |
| parent | 12383f37b2e1d72784e01db0431efc8882f25430 (diff) | |
| download | yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.gz yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.bz2 yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.zip | |
Unify verilog style
Diffstat (limited to 'tests/arch/common/latches.v')
| -rw-r--r-- | tests/arch/common/latches.v | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v index adb5d5319..60b757103 100644 --- a/tests/arch/common/latches.v +++ b/tests/arch/common/latches.v @@ -1,19 +1,16 @@ -module latchp - ( input d, clk, en, output reg q ); +module latchp ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule -module latchn - ( input d, clk, en, output reg q ); +module latchn ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule -module latchsr - ( input d, clk, en, clr, pre, output reg q ); +module latchsr ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; |