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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 14:29:44 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 14:29:44 +0200 |
| commit | e8ef3fcdfcacbc711a4722deee95f0707634bed0 (patch) | |
| tree | 971fae1a1b7d3204827759454fa55accdc9bc01f /tests/arch/common/logic.v | |
| parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
| parent | 190b40341abd73ab5edf0e6740b6526e9575253b (diff) | |
| download | yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.tar.gz yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.tar.bz2 yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.zip | |
Merge pull request #1454 from YosysHQ/mmicko/common_tests
Share common tests
Diffstat (limited to 'tests/arch/common/logic.v')
| -rw-r--r-- | tests/arch/common/logic.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v new file mode 100644 index 000000000..c17899fa0 --- /dev/null +++ b/tests/arch/common/logic.v @@ -0,0 +1,16 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 +); + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; +endmodule |