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| author | Diego H <diego@symbioticeda.com> | 2019-12-15 23:33:09 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-15 23:33:09 -0600 |
| commit | b35559fc335181d7c8f8046fa17bf05550c21ba7 (patch) | |
| tree | 6293cb01ff8137aad0fee27aa575a080b2c2d206 /tests/arch/common/memory_attributes/attributes_test.ys | |
| parent | 266993408a2b926ffefcf536feb92b36b11e398e (diff) | |
| download | yosys-b35559fc335181d7c8f8046fa17bf05550c21ba7.tar.gz yosys-b35559fc335181d7c8f8046fa17bf05550c21ba7.tar.bz2 yosys-b35559fc335181d7c8f8046fa17bf05550c21ba7.zip | |
Merging attribute rules into a single match block; Adding tests
Diffstat (limited to 'tests/arch/common/memory_attributes/attributes_test.ys')
| -rw-r--r-- | tests/arch/common/memory_attributes/attributes_test.ys | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/common/memory_attributes/attributes_test.ys new file mode 100644 index 000000000..4e06a35e7 --- /dev/null +++ b/tests/arch/common/memory_attributes/attributes_test.ys @@ -0,0 +1,47 @@ +# Check that blockram memory without parameters is not modified +read_verilog attributes_test.v +hierarchy -top block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog attributes_test.v +hierarchy -top distributed_ram +synth_xilinx -top distributed_ram +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 8 t:RAM32X1D + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog attributes_test.v +prep +setattr -mod -set ram_style "distributed" block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 32 t:RAM128X1D + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog attributes_test.v +prep +setattr -mod -set logic_block 1 block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 +select -assert-count 32 t:RAM128X1D + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog attributes_test.v +synth_xilinx -top distributed_ram_manual +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram +design -reset +read_verilog attributes_test.v +synth_xilinx -top distributed_ram_manual_syn +cd distributed_ram_manual_syn # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 |