diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
| commit | 9bd9db56c8ef8ca413f97086fd53609c50df343b (patch) | |
| tree | 869984a858e5c9d502ccdfd800618a9c0fe5858a /tests/arch/common/mul.v | |
| parent | 12383f37b2e1d72784e01db0431efc8882f25430 (diff) | |
| download | yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.gz yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.bz2 yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.zip | |
Unify verilog style
Diffstat (limited to 'tests/arch/common/mul.v')
| -rw-r--r-- | tests/arch/common/mul.v | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v index d5b48b1d7..437a91cfc 100644 --- a/tests/arch/common/mul.v +++ b/tests/arch/common/mul.v @@ -1,11 +1,9 @@ module top ( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; + input [5:0] x, + input [5:0] y, + output [11:0] A, +); + assign A = x * y; endmodule |