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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:16:33 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:16:33 +0200 |
| commit | 92e705cb51d8c8f6d9f1550ed103b677a2447c93 (patch) | |
| tree | 7e01e6c2588e9e9a40bdd16ca7dae04a466df478 /tests/arch/common/shifter.v | |
| parent | 72787f52fc31954e4b7dc3dc34d86705fc4e9dd1 (diff) | |
| download | yosys-92e705cb51d8c8f6d9f1550ed103b677a2447c93.tar.gz yosys-92e705cb51d8c8f6d9f1550ed103b677a2447c93.tar.bz2 yosys-92e705cb51d8c8f6d9f1550ed103b677a2447c93.zip | |
Fix files with CRLF line endings
Diffstat (limited to 'tests/arch/common/shifter.v')
| -rw-r--r-- | tests/arch/common/shifter.v | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index cace3b588..3030608ab 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -1,11 +1,11 @@ -module top(out, clk, in);
- output [7:0] out;
- input signed clk, in;
- reg signed [7:0] out = 0;
-
- always @(posedge clk)
- begin
- out <= out >> 1;
- out[7] <= in;
- end
-endmodule
+module top(out, clk, in); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end +endmodule |