Testing TDP synth mapping

New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.

1 files changed, 31 insertions, 0 deletions

diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v
index 5ed0736d0..6b557fdca 100644
--- a/tests/arch/common/blockram.v
+++ b/tests/arch/common/blockram.v
@@ -45,3 +45,34 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
 
 endmodule // sync_ram_sdp
 
+
+`default_nettype none
+module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+   (input  wire                      clk_a, clk_b, 
+    input  wire                      write_enable_a, write_enable_b,
+    input  wire                      read_enable_a, read_enable_b,
+    input  wire  [DATA_WIDTH-1:0]    write_data_a, write_data_b,
+    input  wire  [ADDRESS_WIDTH-1:0] addr_a, addr_b,
+    output reg   [DATA_WIDTH-1:0]    read_data_a, read_data_b);
+
+  localparam WORD  = (DATA_WIDTH-1);
+  localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+  reg [WORD:0] mem [0:DEPTH];
+
+  always @(posedge clk_a) begin
+    if (write_enable_a)
+      mem[addr_a] <= write_data_a;
+    else
+      read_data_a <= mem[addr_a];
+  end
+
+  always @(posedge clk_b) begin
+    if (write_enable_b)
+      mem[addr_b] <= write_data_b;
+    else
+      read_data_b <= mem[addr_b];
+  end
+
+endmodule // sync_ram_tdp
+