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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 12:46:18 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 12:46:18 -0800 |
commit | a855f23f22c9e6dbba5ff17a9541a7d26342b56a (patch) | |
tree | f62715ee5a790615d8d4fcda7814a940608c7310 /tests/arch/ecp5/bug1598.ys | |
parent | f5e0a07ad679696b0d3077ef877941d4c1f864d7 (diff) | |
parent | 7939727d14f44b5d56ca3806d0907e9fceea2882 (diff) | |
download | yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.tar.gz yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.tar.bz2 yosys-a855f23f22c9e6dbba5ff17a9541a7d26342b56a.zip |
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
Diffstat (limited to 'tests/arch/ecp5/bug1598.ys')
-rw-r--r-- | tests/arch/ecp5/bug1598.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/arch/ecp5/bug1598.ys b/tests/arch/ecp5/bug1598.ys new file mode 100644 index 000000000..1d1682fcd --- /dev/null +++ b/tests/arch/ecp5/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9 |