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| author | Eddie Hung <eddie@fpgeh.com> | 2021-09-09 10:05:55 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-09 10:05:55 -0700 |
| commit | f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0 (patch) | |
| tree | 46a0d4a5467a936ae88d56dd310d5c64326798ab /tests/arch/ecp5/bug2731.ys | |
| parent | 50be8fd0c23856be7afa28527fe4f30dcc975c87 (diff) | |
| download | yosys-f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0.tar.gz yosys-f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0.tar.bz2 yosys-f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0.zip | |
abc9: replace cell type/parameters if derived type already processed (#2991)
* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
Diffstat (limited to 'tests/arch/ecp5/bug2731.ys')
| -rw-r--r-- | tests/arch/ecp5/bug2731.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/arch/ecp5/bug2731.ys b/tests/arch/ecp5/bug2731.ys new file mode 100644 index 000000000..c609cea3b --- /dev/null +++ b/tests/arch/ecp5/bug2731.ys @@ -0,0 +1,7 @@ +read_verilog -icells <<EOF +module top(input c, r, input [1:0] d, output reg [1:0] q); +TRELLIS_FF #(.REGSET("SET")) ff1(.CLK(c), .LSR(r), .DI(d[0]), .Q(q[0])); +TRELLIS_FF #(.REGSET("SET")) ff2(.CLK(c), .LSR(r), .DI(d[1]), .Q(q[1])); +endmodule +EOF +synth_ecp5 -abc9 -dff |