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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:21 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:21 -0800 |
| commit | a73f96594f4688afc85098b485ef7788e79f5c33 (patch) | |
| tree | 8b4fdf160bcb8a8db62a309fd409096a721bb3c7 /tests/arch/ecp5/lutram.ys | |
| parent | 9935370ada858da56b5d61a3806768af11565a47 (diff) | |
| parent | 5d009964266e3b52a01c72ee930601d0ebf3a838 (diff) | |
| download | yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.gz yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.bz2 yosys-a73f96594f4688afc85098b485ef7788e79f5c33.zip | |
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
Diffstat (limited to 'tests/arch/ecp5/lutram.ys')
| -rw-r--r-- | tests/arch/ecp5/lutram.ys | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/arch/ecp5/lutram.ys b/tests/arch/ecp5/lutram.ys new file mode 100644 index 000000000..e1ae7abd5 --- /dev/null +++ b/tests/arch/ecp5/lutram.ys @@ -0,0 +1,19 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D |