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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 14:55:57 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-05 14:55:57 -0800 |
| commit | 6eb7e925a12ea20192aa7caf7857a6742af8471e (patch) | |
| tree | 5c8f0e7377db8e21ed8d9a77375d8c2ef55b3292 /tests/arch/ecp5/mux.ys | |
| parent | 0b308c68357cc85876c3c86d6e5ac8b9318329ca (diff) | |
| parent | b6a1f627b5871e750fe6a559fbb42334c7de8b84 (diff) | |
| download | yosys-6eb7e925a12ea20192aa7caf7857a6742af8471e.tar.gz yosys-6eb7e925a12ea20192aa7caf7857a6742af8471e.tar.bz2 yosys-6eb7e925a12ea20192aa7caf7857a6742af8471e.zip | |
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
techmap LSB-first for compatible $shift/$shiftx cells
Diffstat (limited to 'tests/arch/ecp5/mux.ys')
| -rw-r--r-- | tests/arch/ecp5/mux.ys | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 22866832d..92463aa32 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -39,8 +39,8 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 12 t:L6MUX21 -select -assert-count 34 t:LUT4 -select -assert-count 17 t:PFUMX +select -assert-count 8 t:L6MUX21 +select -assert-count 26 t:LUT4 +select -assert-count 12 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D |