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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 10:29:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 10:29:40 -0800 |
| commit | 94f15f023c8720d84211ac75980cf0b0f492411d (patch) | |
| tree | 29f40490883b15fec68ef6aba99767a0deaecc4f /tests/arch/ecp5 | |
| parent | 76ba06a79ea917a0e515aa0e99ae41f42e8bddc9 (diff) | |
| parent | f52c6efd9da161e625538f9e8c23875efebda60f (diff) | |
| download | yosys-94f15f023c8720d84211ac75980cf0b0f492411d.tar.gz yosys-94f15f023c8720d84211ac75980cf0b0f492411d.tar.bz2 yosys-94f15f023c8720d84211ac75980cf0b0f492411d.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/arch/ecp5')
| -rw-r--r-- | tests/arch/ecp5/lutram.ys (renamed from tests/arch/ecp5/memory.ys) | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/lutram.ys index c82b7b405..e1ae7abd5 100644 --- a/tests/arch/ecp5/memory.ys +++ b/tests/arch/ecp5/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 @@ -10,7 +10,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 24 t:L6MUX21 select -assert-count 71 t:LUT4 select -assert-count 32 t:PFUMX |