Merge remote-tracking branch 'origin/master' into xaig_dff

13 files changed, 259 insertions, 0 deletions

diff --git a/tests/arch/efinix/.gitignore b/tests/arch/efinix/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/arch/efinix/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/arch/efinix/add_sub.ys b/tests/arch/efinix/add_sub.ys
new file mode 100644
index 000000000..20523c059
--- /dev/null
+++ b/tests/arch/efinix/add_sub.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 10 t:EFX_ADD
+select -assert-count 4  t:EFX_LUT4
+select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
+
diff --git a/tests/arch/efinix/adffs.ys b/tests/arch/efinix/adffs.ys
new file mode 100644
index 000000000..49dc7f256
--- /dev/null
+++ b/tests/arch/efinix/adffs.ys
@@ -0,0 +1,50 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys
new file mode 100644
index 000000000..d20b8ae27
--- /dev/null
+++ b/tests/arch/efinix/counter.ys
@@ -0,0 +1,12 @@
+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 8 t:EFX_FF
+select -assert-count 9 t:EFX_ADD
+select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D
diff --git a/tests/arch/efinix/dffs.ys b/tests/arch/efinix/dffs.ys
new file mode 100644
index 000000000..af787ab67
--- /dev/null
+++ b/tests/arch/efinix/dffs.ys
@@ -0,0 +1,24 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys
new file mode 100644
index 000000000..a2db2ad98
--- /dev/null
+++ b/tests/arch/efinix/fsm.ys
@@ -0,0 +1,16 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 1  t:EFX_GBUFCE
+select -assert-count 6  t:EFX_FF
+select -assert-count 15 t:EFX_LUT4
+select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys
new file mode 100644
index 000000000..1b1c00023
--- /dev/null
+++ b/tests/arch/efinix/latches.ys
@@ -0,0 +1,33 @@
+read_verilog ../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_efinix
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_efinix
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_efinix
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys
new file mode 100644
index 000000000..76e98e079
--- /dev/null
+++ b/tests/arch/efinix/logic.ys
@@ -0,0 +1,9 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 9 t:EFX_LUT4
+select -assert-none t:EFX_LUT4 %% t:* %D
diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys
new file mode 100644
index 000000000..6f6acdcde
--- /dev/null
+++ b/tests/arch/efinix/memory.ys
@@ -0,0 +1,18 @@
+read_verilog ../common/memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Called with -verify and proof did fail!
+#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_RAM_5K
+select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys
new file mode 100644
index 000000000..b46f641e1
--- /dev/null
+++ b/tests/arch/efinix/mux.ys
@@ -0,0 +1,41 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 12 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
diff --git a/tests/arch/efinix/run-test.sh b/tests/arch/efinix/run-test.sh
new file mode 100755
index 000000000..bf19b887d
--- /dev/null
+++ b/tests/arch/efinix/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/arch/efinix/shifter.ys b/tests/arch/efinix/shifter.ys
new file mode 100644
index 000000000..54f71167f
--- /dev/null
+++ b/tests/arch/efinix/shifter.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1  t:EFX_GBUFCE
+select -assert-count 8  t:EFX_FF
+select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D
diff --git a/tests/arch/efinix/tribuf.ys b/tests/arch/efinix/tribuf.ys
new file mode 100644
index 000000000..47904f2d5
--- /dev/null
+++ b/tests/arch/efinix/tribuf.ys
@@ -0,0 +1,12 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+#Internal cell type used. Need support it.
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D