diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 14:55:57 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-05 14:55:57 -0800 |
| commit | 6eb7e925a12ea20192aa7caf7857a6742af8471e (patch) | |
| tree | 5c8f0e7377db8e21ed8d9a77375d8c2ef55b3292 /tests/arch/efinix | |
| parent | 0b308c68357cc85876c3c86d6e5ac8b9318329ca (diff) | |
| parent | b6a1f627b5871e750fe6a559fbb42334c7de8b84 (diff) | |
| download | yosys-6eb7e925a12ea20192aa7caf7857a6742af8471e.tar.gz yosys-6eb7e925a12ea20192aa7caf7857a6742af8471e.tar.bz2 yosys-6eb7e925a12ea20192aa7caf7857a6742af8471e.zip | |
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
techmap LSB-first for compatible $shift/$shiftx cells
Diffstat (limited to 'tests/arch/efinix')
| -rw-r--r-- | tests/arch/efinix/mux.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index a5ab80d8b..67006b6f2 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -16,7 +16,7 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:EFX_LUT4 +#select -assert-count 2 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D @@ -26,7 +26,7 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:EFX_LUT4 +#select -assert-count 5 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D |