diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:21 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:21 -0800 |
| commit | a73f96594f4688afc85098b485ef7788e79f5c33 (patch) | |
| tree | 8b4fdf160bcb8a8db62a309fd409096a721bb3c7 /tests/arch/efinix | |
| parent | 9935370ada858da56b5d61a3806768af11565a47 (diff) | |
| parent | 5d009964266e3b52a01c72ee930601d0ebf3a838 (diff) | |
| download | yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.gz yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.bz2 yosys-a73f96594f4688afc85098b485ef7788e79f5c33.zip | |
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
Diffstat (limited to 'tests/arch/efinix')
| -rw-r--r-- | tests/arch/efinix/lutram.ys (renamed from tests/arch/efinix/memory.ys) | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/lutram.ys index 6f6acdcde..dcf647ce0 100644 --- a/tests/arch/efinix/memory.ys +++ b/tests/arch/efinix/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix @@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_RAM_5K select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D |