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| author | Patrick Urban <patrick.urban@web.de> | 2021-09-13 17:16:15 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-13 21:53:25 +0100 |
| commit | 240d289ffff69f991e096a630028839048b6fefd (patch) | |
| tree | fb79233fbfae812d9c4723b7cd50a7869e5f1850 /tests/arch/gatemate/add_sub.ys | |
| parent | b3e2001e1f094eccf925f0b9e88b3d7cae5e5cb0 (diff) | |
| download | yosys-240d289ffff69f991e096a630028839048b6fefd.tar.gz yosys-240d289ffff69f991e096a630028839048b6fefd.tar.bz2 yosys-240d289ffff69f991e096a630028839048b6fefd.zip | |
synth_gatemate: Initial implementation
Signed-off-by: Patrick Urban <patrick.urban@web.de>
Diffstat (limited to 'tests/arch/gatemate/add_sub.ys')
| -rw-r--r-- | tests/arch/gatemate/add_sub.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys new file mode 100644 index 000000000..c0055e521 --- /dev/null +++ b/tests/arch/gatemate/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:CC_ADDF +select -assert-count 4 t:CC_LUT1 +select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D |