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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-19 17:29:27 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-19 17:29:27 +0100 |
| commit | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (patch) | |
| tree | 7825f438b83fdc730764ba15016eeeac9eb0cf41 /tests/arch/gowin/logic.ys | |
| parent | 15232a48af60fb7da3c3afdd144882ace2194197 (diff) | |
| parent | 8ab412eb16b1d4f98117247bf85e0c37627ee459 (diff) | |
| download | yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.gz yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.bz2 yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.zip | |
Merge pull request #1449 from pepijndevos/gowin
Improvements for gowin support
Diffstat (limited to 'tests/arch/gowin/logic.ys')
| -rw-r--r-- | tests/arch/gowin/logic.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/arch/gowin/logic.ys b/tests/arch/gowin/logic.ys new file mode 100644 index 000000000..d2b9e4540 --- /dev/null +++ b/tests/arch/gowin/logic.ys @@ -0,0 +1,13 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT4 +select -assert-count 8 t:IBUF +select -assert-count 10 t:OBUF +select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D |