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authorN. Engelhardt <nak@symbioticeda.com>2020-01-03 12:28:48 +0100
committerN. Engelhardt <nak@symbioticeda.com>2020-01-03 12:28:48 +0100
commit341fd872b59e8f95aa14afd9f17225d2c03a4283 (patch)
tree21802e73ca767d124971d43d3f78d9f4cf7d62e2 /tests/arch/gowin
parentc8bc1793a4e8230c29fca4a34862414e8ab8722b (diff)
parentf8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3 (diff)
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Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script
Diffstat (limited to 'tests/arch/gowin')
-rw-r--r--tests/arch/gowin/counter.ys2
-rw-r--r--tests/arch/gowin/lutram.ys (renamed from tests/arch/gowin/memory.ys)6
2 files changed, 4 insertions, 4 deletions
diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys
index 920479d44..bdbc7ee24 100644
--- a/tests/arch/gowin/counter.ys
+++ b/tests/arch/gowin/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
-equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/lutram.ys
index 8f88cdd7c..56f69e7c5 100644
--- a/tests/arch/gowin/memory.ys
+++ b/tests/arch/gowin/lutram.ys
@@ -1,5 +1,5 @@
-read_verilog ../common/memory.v
-hierarchy -top top
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
@@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
-cd top
+cd lutram_1w1r
select -assert-count 8 t:RAM16S4
# other logic present that is not simple
#select -assert-none t:RAM16S4 %% t:* %D