diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
| commit | 5603595e5c0efd2afc9ba810e6e5992e5d81d44c (patch) | |
| tree | dcf99c611410e055a7ea71c970938ed6ee50a3c6 /tests/arch/ice40/dffs.ys | |
| parent | ab98f2dccf52a1bba396fe313ea0670603dc45ca (diff) | |
| download | yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.gz yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.bz2 yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.zip | |
Share common tests
Diffstat (limited to 'tests/arch/ice40/dffs.ys')
| -rw-r--r-- | tests/arch/ice40/dffs.ys | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys index ee7f884b1..b28a5a91f 100644 --- a/tests/arch/ice40/dffs.ys +++ b/tests/arch/ice40/dffs.ys @@ -1,10 +1,19 @@ -read_verilog dffs.v -hierarchy -top top +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff proc -flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFFE -select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D +select -assert-none t:SB_DFFE %% t:* %D
\ No newline at end of file |