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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:20:35 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:20:35 +0200 |
| commit | 477702b8c91bb7780ac80b25c8ad659cd40b445d (patch) | |
| tree | 8d11b79822187dbac8b03c7314eb6b4d8959a7f1 /tests/arch/ice40/div_mod.ys | |
| parent | 5603595e5c0efd2afc9ba810e6e5992e5d81d44c (diff) | |
| download | yosys-477702b8c91bb7780ac80b25c8ad659cd40b445d.tar.gz yosys-477702b8c91bb7780ac80b25c8ad659cd40b445d.tar.bz2 yosys-477702b8c91bb7780ac80b25c8ad659cd40b445d.zip | |
Remove not needed tests
Diffstat (limited to 'tests/arch/ice40/div_mod.ys')
| -rw-r--r-- | tests/arch/ice40/div_mod.ys | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys deleted file mode 100644 index 821d6c301..000000000 --- a/tests/arch/ice40/div_mod.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 59 t:SB_LUT4 -select -assert-count 41 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D |