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authorEddie Hung <eddie@fpgeh.com>2019-11-19 15:40:39 -0800
committerEddie Hung <eddie@fpgeh.com>2019-11-19 15:40:39 -0800
commit09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch)
tree8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/arch/ice40/dpram.v
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parent7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff)
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Merge remote-tracking branch 'origin/master' into xaig_dff
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+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
+*/
+module top (din, write_en, waddr, wclk, raddr, rclk, dout);
+parameter addr_width = 8;
+parameter data_width = 8;
+input [addr_width-1:0] waddr, raddr;
+input [data_width-1:0] din;
+input write_en, wclk, rclk;
+output [data_width-1:0] dout;
+reg [data_width-1:0] dout;
+reg [data_width-1:0] mem [(1<<addr_width)-1:0]
+/* synthesis syn_ramstyle = "no_rw_check" */ ;
+always @(posedge wclk) // Write memory.
+begin
+if (write_en)
+mem[waddr] <= din; // Using write address bus.
+end
+always @(posedge rclk) // Read memory.
+begin
+dout <= mem[raddr]; // Using read address bus.
+end
+endmodule