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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
| commit | c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch) | |
| tree | 79cce7951390a0068beeab26be5d310222059c51 /tests/arch/ice40/dpram.ys | |
| parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
| download | yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.gz yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.bz2 yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.zip | |
Moved all tests in arch sub directory
Diffstat (limited to 'tests/arch/ice40/dpram.ys')
| -rw-r--r-- | tests/arch/ice40/dpram.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/arch/ice40/dpram.ys b/tests/arch/ice40/dpram.ys new file mode 100644 index 000000000..4f6a253ea --- /dev/null +++ b/tests/arch/ice40/dpram.ys @@ -0,0 +1,15 @@ +read_verilog dpram.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:SB_RAM40_4K +select -assert-none t:SB_RAM40_4K %% t:* %D |