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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
| commit | 5603595e5c0efd2afc9ba810e6e5992e5d81d44c (patch) | |
| tree | dcf99c611410e055a7ea71c970938ed6ee50a3c6 /tests/arch/ice40/fsm.ys | |
| parent | ab98f2dccf52a1bba396fe313ea0670603dc45ca (diff) | |
| download | yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.gz yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.bz2 yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.zip | |
Share common tests
Diffstat (limited to 'tests/arch/ice40/fsm.ys')
| -rw-r--r-- | tests/arch/ice40/fsm.ys | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index 4cc8629d6..5aacc6c73 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -1,10 +1,10 @@ -read_verilog fsm.v -hierarchy -top top +read_verilog ../common/fsm.v +hierarchy -top fsm proc flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 2 t:SB_DFFESR select -assert-count 2 t:SB_DFFSR |