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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-07-07 10:27:54 +1200 |
|---|---|---|
| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2023-02-21 05:23:15 +1300 |
| commit | af1b9c9e070dd5873871c73c5762fbefd345a8c9 (patch) | |
| tree | fb128b5f96effbfe90a8efd239da411f8052d2f7 /tests/arch/ice40/spram.v | |
| parent | de2f140c090742ec8ccded4cfacc2dc6bac2a562 (diff) | |
| download | yosys-af1b9c9e070dd5873871c73c5762fbefd345a8c9.tar.gz yosys-af1b9c9e070dd5873871c73c5762fbefd345a8c9.tar.bz2 yosys-af1b9c9e070dd5873871c73c5762fbefd345a8c9.zip | |
Tests for ram_style = "huge"
iCE40 SPRAM and Xilinx URAM
Diffstat (limited to 'tests/arch/ice40/spram.v')
| -rw-r--r-- | tests/arch/ice40/spram.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/arch/ice40/spram.v b/tests/arch/ice40/spram.v new file mode 100644 index 000000000..4e1aef2c6 --- /dev/null +++ b/tests/arch/ice40/spram.v @@ -0,0 +1,22 @@ +module top (clk, write_enable, read_enable, write_data, addr, read_data); +parameter DATA_WIDTH = 8; +parameter ADDR_WIDTH = 8; +parameter SKIP_RDEN = 1; + +input clk; +input write_enable, read_enable; +input [DATA_WIDTH - 1 : 0] write_data; +input [ADDR_WIDTH - 1 : 0] addr; +output [DATA_WIDTH - 1 : 0] read_data; + +(* ram_style = "huge" *) +reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + +always @(posedge clk) begin + if (write_enable) + mem[addr] <= write_data; + else if (SKIP_RDEN || read_enable) + read_data <= mem[addr]; +end + +endmodule |