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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-01 13:31:46 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-01 13:31:46 -0800 |
| commit | 9e5ff30d0524629a1713d2e4cf92bbd9adffa857 (patch) | |
| tree | 94bf37fbb163466a874286e6295f3fd9aefc7132 /tests/arch/ice40 | |
| parent | 6620b4e94e106340ca10d5602c32bfd0313ff46e (diff) | |
| parent | 52fe1e0c44d572b8e1f8881dc0a1e91f7fa93c9c (diff) | |
| download | yosys-9e5ff30d0524629a1713d2e4cf92bbd9adffa857.tar.gz yosys-9e5ff30d0524629a1713d2e4cf92bbd9adffa857.tar.bz2 yosys-9e5ff30d0524629a1713d2e4cf92bbd9adffa857.zip | |
Merge pull request #1606 from YosysHQ/eddie/improve_tests
Fix a few issues in tests/arch/*
Diffstat (limited to 'tests/arch/ice40')
| -rw-r--r-- | tests/arch/ice40/counter.ys | 2 | ||||
| -rw-r--r-- | tests/arch/ice40/mul.ys | 2 | ||||
| -rw-r--r-- | tests/arch/ice40/rom.v | 3 |
3 files changed, 4 insertions, 3 deletions
diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys index f112eb97d..7bbc4f2c3 100644 --- a/tests/arch/ice40/counter.ys +++ b/tests/arch/ice40/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 6 t:SB_CARRY diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys index 9891b77d6..b8c3eb941 100644 --- a/tests/arch/ice40/mul.ys +++ b/tests/arch/ice40/mul.ys @@ -1,6 +1,6 @@ read_verilog ../common/mul.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_MAC16 diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v index 0a0f41f37..71459fe38 100644 --- a/tests/arch/ice40/rom.v +++ b/tests/arch/ice40/rom.v @@ -2,7 +2,8 @@ Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. */ module top(data, addr); -output [3:0] data; +output [3:0] data; // Note: this prompts a Yosys warning, but + // vendor doc does not contain 'reg' input [4:0] addr; always @(addr) begin case (addr) |