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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-05 18:53:14 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 21:36:38 +0200 |
| commit | 0d4c2f0a65de2fccd767a56b9698be3d913fdd9f (patch) | |
| tree | 1a893fd344cc7be071d175c9183bb9d10ffa89a5 /tests/arch/intel_alm/quartus_ice.ys | |
| parent | b5f3b70cfeed9421e6d0daa3a1ef968b2b670bc2 (diff) | |
| download | yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.tar.gz yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.tar.bz2 yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.zip | |
intel_alm: add Cyclone 10 GX tests
Diffstat (limited to 'tests/arch/intel_alm/quartus_ice.ys')
| -rw-r--r-- | tests/arch/intel_alm/quartus_ice.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys index 4b9b54d10..a88226e13 100644 --- a/tests/arch/intel_alm/quartus_ice.ys +++ b/tests/arch/intel_alm/quartus_ice.ys @@ -10,3 +10,17 @@ EOT synth_intel_alm -family cyclonev -quartus select -assert-none w:*[* w:*]* + +design -reset +read_verilog <<EOT +// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space. +// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier. +module top(); + (* keep *) wire [31:0] \a[10] ; + (* keep *) wire b; + assign b = \a[10] [31]; +endmodule +EOT + +synth_intel_alm -family cyclone10gx -quartus +select -assert-none w:*[* w:*]* |